Departmentof Electrical and Computer Engineering
Digital Design Principles
ECE
Prof.Volkan Rodoplu
Lectures:Monday/Wednesday at LSB 1001.
Professor'sOffice hours: , Mondays and Wednesdays,
in Room 4113, Harold FrankHall; starting
Syllabus
MidtermExam:inclass, see course calendar in Syllabus
FinalExam:Lookup in the Course Offerings schedule of final exams.
Announcements
| 02/13/08: Prof. Rodoplu will not have regular office hours on the following dates: Feb. 18 (holiday), Feb. 20 (Midterm), Feb. 25 (out of town). 01/11/08: For HW #1, Problem # 8 of the Course Reader: If you have found the minimum SOP expression for each of the outputs of this circuit, and yet your implementation uses more than 11 gates, this is fine. We will give you full credit. 01/11/08: Please read the UCSB/ECE FPGA Board web page: http://vader.ece.ucsb.edu/digilab-fpga/ 01/11/08: For Lab # 1: Please note that NOT all TTL parts are available. See the hyperlink below on ECE Shop: List of Available Parts (under Lab Handouts). Only these chips are available in the lab, so plan your TTL implementation accordingly. 01/11/08: Please use TTL (7400 series) for your labs (not CMOS 4000 series parts!). 01/11/08: For the pre-labs, you need to hand in only 1 solution per team (put both team members' names on your solutions.) 01/11/08: Check in the ECE Shop (Room: 1160, Harold Frank Hall; M-F: 8:00-12:00 and 1:00-4:00) to get the access cards for the Digital lab. |
CourseReader
(Homework is assigned from the reader.)
CourseReader_Problems 10 to 14
CourseReader Problems 18
CourseReader Problems 19-20
CourseReaderProblems 32-33
Homework - Solutions
The homework is due in the ECE
(After you exit the elevator, go straightthrough the double doors across from you. The homework box is outside after yougo through the double doors.)
| HW # 1 (due February 1, 2008; 2:00 PM) For HW # 1, PLEASE SKIP PROBLEM # 6. DO THE REST OF THE PROBLEMS. | HW # 2 (due February 8, 2008; 2:00 PM) For HW # 2: PLEASE SKIP PROBLEMS 3, AND 9. (These are B & V Problem 7.32, and Problem # DO THE REST OF THE PROBLEMS. |
| HW # 3 (due February 29, 2008, 2:00 PM) For HW # 3: PLEASE SKIP PROBLEMS 1-3 (the B&V textbook problems). Do the REST of the Problems, which are from the Course Reader. (Start early!) | HW # 4 (due March 7, 2008, 2:00 PM) |
| HW # 5 (due March 14, 2008; Friday, 2:00 PM) | |
Grading Guidelines for Homeworks and Labs
Lab Handouts
Lab Schedule
Print out Data Sheetsfor each lab
ECEShop: List of Available Parts
UCSB/ECEDigiLab FPGA Board Information
ALL PRE-LABS DUE ARE AT THE BEGINNING OF YOUR LAB.
THE CHECK-OUTS FOR DEMOS MUST BE DONE WITHIN FIRST 1 HR. OFTHE LAB SECTION.
All the lab dates below are for"week of" the date indicated,
at the beginning of your lab section.
| Lab #1 Nothing is due: January 14, 2008 (but highly encouraged to complete as much of Steps # 1 and # 2 as possible.) Pre-lab due: (Steps # 1 and # 2 due) January 21, 2008. [Demo of Steps # 3 and/or # 4 encouraged, but not required.] Check-out (Steps # 3 and # 4): January 28, 2008 | Lab #2 Pre-lab due: January 28, 2008 [This is a long pre-lab; start early!] Check-out: February 4, 2008 |
| Lab #3 Lab starts: Check-out: (Hint: Use teamwork to manage the wiring to get it done by the deadline.) | Lab # 4 Lab-4 help Sample C program cbw.h cbw32bc.lib lab4_verilog Sample-Testbench cbw32.dll Lab starts: (There is no pre-lab for this lab.) Part 1 due: Parts 2, 3 and 4 due: February 25, 2008 |
| Lab #5 template.v Lab starts: (There is no pre-lab for this lab.) Parts 1 and 2 due: Parts 3 and 4 due: March 10, 2008 |
LabSections and TA Office Hours
HaroldFrank Hall, Room 1124 (DigiLab)
You may go to theoffice hours of any TA (not just the TA of your lab section)
| Kunal Arya karya@umail.ucsb.edu Lab Section: Wed: 7:00 - 9:50 pm Office hours: Wed: 5:30 - 7:00 pm | Sheng-Luen Wei ("Vincent") swei@umail.ucsb.edu Lab Section: Tue: 7:00 - 9:50 pm Office hours: Tue: 4:30 – 6:00 pm |
Acknowledgments: We would like to thank allthe professors, TA's and lecturers, who have created, worked on, used, andrevised the laboratories for this course. A partial list is as follows: Prof.Roger C. Wood, Christian Schmidt, Prof. Kaustav Banerjee, James Rosenthal,Brian Simolon, Dr. John M. Johnson, Prof. Volkan Rodoplu, Aida Todri, NileshModi, Vishal Mehta, James Tandon. We would also like to thank Dr. John M.Johnson for preparing lecture note slides for this course, and for hiscontinuing contributions during the summer quarters.
Practice Exams
ECE 152A Midterm Exam Fall 2004
ECE152A_Midterm Exam Winter 2005
ECE 152A Midterm Exam Fall 2005
ECE 152A Midterm Exam Fall 2007
ECE 152A Midterm Exam Winter 2008
ECE 152A Final Exam Fall 2004
ECE 152A Final Exam Winter 2005
Practice Problems for FSM Design: PS1 PS2 PS4
Lecture Notes (veryrough)
(The following arehandwritten lecture notes that I made while preparing for the lectures. Theseare very rough compared to the exposition in class, and were mostly notes tomyself. However, I am providing them here in case you find them useful.)
. Lecture 0
. Lecture 1
. Lecture 2
. Lecture 3
. Lecture 4
. Lectures 5-6
. Lecture 5-6 Addendum
. Lecture 7
. Lecture 8-9
. FSM Examples
. Mealy/MooreExamples
. Blocking vs.Non-blocking Assignments
. Lecture 11
. Timing_Supplement1
. Timing_Supplement2
. Lecture 13
. CMOSLecture Slides
. Lecture 14
. Lecture 14.2 (Adders # 2)
. Final Exam Review Lecture
. (Enrichment (not required): Lecture 10)
Lecture Slides (preparedby Prof. Johnson)
Lecture 1
Lecture 2
Lecture 3
[Lecture 14]
Lecture 4
(Lecture 4 Supplement)
Lecture 5
Lecture 6
Lecture 7
Lecture 8
Lecture 9
Lecture 10
Lecture 11
Lecture 12
Lecture 13
Lecture 15
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